2

An all-digital phase-locked loop for high-speed clock generation

Year:
2003
Language:
english
File:
PDF, 414 KB
english, 2003
13

A 90

Year:
2011
Language:
english
File:
PDF, 976 KB
english, 2011
24

A new DLL-based approach for all-digital multiphase clock generation

Year:
2004
Language:
english
File:
PDF, 501 KB
english, 2004
45

A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems

Year:
2008
Language:
english
File:
PDF, 856 KB
english, 2008